When high-speed and low voltage swing data transfer is needed, differential signaling (also commonly referred to as double ended signals), wherein signals are carried on two conductors and the signal is defined as the difference in the two signals. Differential signaling is perhaps the most robust and promising signaling concept. Current mode logic (CML), a design technique commonly used in high speed signaling applications such as communications chips and routers, uses differential signaling.
CML is widely used in high-speed applications due to its relatively low power consumption and low supply voltage when compared to other types of logic, such as emitter coupled logic (ECL). CML is also considerably faster than CMOS logic due to its lower voltage swings. CML also has an added advantage of the capability of being fabricated using CMOS fabrication technology.
One advantage that CMOS logic has over CML is that in a CML circuit, there can be current flow a standby state, while in CMOS logic, no current flows in the standby state. Therefore, CML circuits will typically use more power than CMOS logic circuits.
However, since CML circuits and CMOS logic circuits may be created on the same substrate, it is possible to combine CML and CMOS logic circuits into one design. Thus, the high-speed advantages of CML circuits may be exploited where there is a need for high-speed switching, while CMOS logic's low power consumption is available when the utmost high-speed is not required.
Unfortunately, CML circuits use differential signaling while CMOS logic circuits use single ended signals, wherein signals are carried on a single conductor. Therefore, a conversion between a CMOS logic circuit's single ended signals to a CML circuit's differential signals is needed.
A commonly used solution uses a single ended mode to differential mode converter to perform the conversion from single ended signals into differential mode signals. The solution uses a simple inverter to provide a signal and its inverse.
A disadvantage of the prior art is that the simple inverter places a gate delay into the inverse of the input signal that is not present in the input signal itself. The timing mismatched signals may result in a situation wherein both portions of a CML circuit being turned on or turned off. This leads to a poor CML slope which can have detrimental effects on the performance (such as maximum operating frequency) of the circuitry.